Computer systems include a number of components and elements, which are typically coupled via a bus or interconnect. Previously, input/output (IO) devices were coupled together through a conventional multi-drop parallel bus architecture referred to as Peripheral Component Interconnect (PCI). More recently, a new generation of an IO bus referred to as PCI-Express (PCIe) has been used to facilitate faster interconnection between devices having a serial physical layer communication protocol.
A PCIe architecture includes a layered protocol to communicate between devices. As an example, a physical layer, link layer, and transaction layer form a PCIe protocol stack. The PCIe link is built around dedicated unidirectional pairs of serial point-to-point connections referred to as a lane. A link between devices includes some number of lanes, such as one, two, sixteen, thirty-two, and so-on. The current PCIe specification, PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007), is available at http://www.pcisig.com/specifications/pciexpress/.
A PCIe protocol utilizes credit-based flow control mechanisms to transfer packets across a link. The receiver advertises credits equal to the amount of storage buffers available at the receiver. The transmitter is not permitted to issue transactions that can consume more credits than what the receiver has advertised. The payload length supplied in the transmitter request header is required to match exactly to the amount of data payload supplied and be less than or equal to credits available at the receiver in order to service the transaction. This can unnecessarily limit flexibility in data communication.